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NVIDIA NCP-AII : NVIDIA AI Infrastructure

NCP-AII real exams

Exam Code: NCP-AII

Exam Name: NVIDIA AI Infrastructure

Updated: Sep 01, 2025

Q & A: 301 Questions and Answers

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NVIDIA AI Infrastructure Sample Questions:

1. Which of the following are key considerations when choosing between CPU pinning and NUMA (Non-Uniform Memory Access) awareness for a distributed training job on a multi-socket AMD EPYC server with multiple GPUs?

A) Neither CPU pinning nor NUMA awareness are relevant for GPIJ-accelerated workloads, as the GPUs handle all the computation.
B) Both CPU pinning and NUMA awareness are critical for optimizing performance. They should be used in conjunction to achieve optimal performance.
C) CPU pinning is generally more important than NIJMA awareness because it directly impacts CPU utilization.
D) CPU pinning ensures that each process/thread runs on a specific CPU core, reducing context switching overhead. NUMA awareness ensures that the CPU cores and memory used by a process are located within the same NUMA node, minimizing memory access latency.
E) NUMA awareness is generally more important than CPU pinning because it directly impacts memory bandwidth.


2. You are designing a large-scale AI training cluster spanning multiple racks. The networking topology necessitates both short-reach (within rack) and long-reach (inter-rack) connections. Which combination of cable types and transceivers is MOST cost-effective and suitable for this scenario, assuming a mix of 200GbE and 400GbE links?

A) Passive copper cables for all intra-rack connections and ER4 transceivers with single-mode fiber for all inter-rack connections.
B) DAC cables for all intra-rack connections and FR4 transceivers with single-mode fiber for inter-rack connections.
C) AOC cables for all connections, both intra-rack and inter-rack.
D) DAC cables for all intra-rack connections and AOC cables for all inter-rack connections.
E) DAC cables for all intra-rack connections, and a mix of SR4 and LR4 transceivers with multimode and single-mode fiber, respectively, for inter-rack connections.


3. You are observing that the memory bandwidth being achieved by your CUDA application on an NVIDIAAIOO GPU is significantly lower than the theoretical peak bandwidth. Which of the following could be potential causes for this, and what actions can you take to validate or mitigate them? (Select all that apply)

A) The GPU is being limited by power capping. Increase the power limit using 'nvidia-smi -pl' (if permitted) to allow the GPU to operate at higher clock speeds.
B) The application is using uncoalesced memory access patterns. Refactor the code to ensure contiguous memory access by threads within a warp.
C) The system memory is fully occupied. Deallocate some memory.
D) The application is using a small transfer size per kernel launch. Increase the amount of data processed per kernel launch to amortize the overhead of kernel launch and data transfer.
E) The application is using single precision floating-point operations. Switch to double precision to increase memory bandwidth utilization.


4. You're optimizing an Intel Xeon server with 4 NVIDIAAIOO GPUs for a computer vision application that uses CODA. You notice that the GPU utilization is fluctuating significantly, and performance is inconsistent. Using 'nvprof, you identify that there are frequent stalls in the CUDA kernels due to thread divergence. What are possible causes and solutions?

A) The CUDA compiler is generating suboptimal code. Try using different compiler optimization flags (e.g., '-O3' or '-ftz=true').
B) The CUDA driver version is incompatible with the CUDA toolkit version. Update the CUDA driver to a compatible version.
C) The input data is not properly aligned in memory. Ensure that data is aligned to 128-byte boundaries using aligned memory allocation techniques.
D) The GPUs are overheating, causing thermal throttling. Improve the server's cooling.
E) The CUDA code contains conditional branches that lead to different execution paths for different threads within the same warp. Rewrite the CUDA code to minimize branching and favor uniform execution paths within warps.


5. A data scientist reports that training performance on a DGX A100 server has significantly degraded over the past week. 'nvidia-smi' shows all GPUs functioning, but 'nvprof' reveals substantially increased 'cudaMemcpy' times. What is the MOST likely bottleneck?

A) The CPU is heavily loaded, causing contention for system memory bandwidth.
B) The PCle bus is saturated, limiting data transfer speeds between the CPU and GPUs.
C) The storage system is slow, delaying data loading and preprocessing.
D) The GPUs are overheating, causing thermal throttling and slower memory transfers.
E) The NVLink connections between GPUs are failing, forcing data transfers through PCle.


Solutions:

Question # 1
Answer: B,D
Question # 2
Answer: E
Question # 3
Answer: A,B,D
Question # 4
Answer: C,E
Question # 5
Answer: A

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